By Olivier Jamin
This e-book discusses the trade-offs interested in designing direct RF digitization receivers for the radio frequency and electronic sign processing domain names. A system-level framework is built, quantifying the correct impairments of the sign processing chain, via a complete system-level research. distinctive concentration is given to noise research (thermal noise, quantization noise, saturation noise, signal-dependent noise), broadband non-linear distortion research, together with the impression of the sampling technique (low-pass, band-pass), research of time-interleaved ADC channel mismatches, sampling clock purity and electronic channel choice. The system-level framework defined is utilized to the layout of a cable multi-channel RF direct digitization receiver. An optimal RF sign conditioning, and a few algorithms (automatic achieve keep an eye on loop, RF front-end amplitude equalization keep an eye on loop) are used to sit back the necessities of a 2.7GHz 11-bit ADC.
A two-chip implementation is gifted, utilizing BiCMOS and 65nm CMOS procedures, including the block and system-level size effects. Readers will enjoy the options provided, that are hugely aggressive, either by way of rate and RF functionality, whereas greatly lowering strength consumption.
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1006 0 2 4 6 8 14 10 12 SNRIMP-SNRQEF[dB] 16 18 20 Fig. 9 Implementation loss against delta SNR Fig. 9) where Δ is the step size of the quantizer. The input signals, output signals, and quantization errors are illustrated in Fig. 10, both in case of a ramp and sine wave input signals. 48 2 System-Level Design Framework for Direct RF Digitization RX x[n] y[n] eq[n] Fig. 11) A useful model of a quantizer is depicted in Fig. 11. The model is exact if e[n] is known. However, in most cases, e[n] is not known, because of input signal complexity, and a statistical model based on Fig.
In addition, I/Q digital calibration techniques can keep this effect under control . In case the homodyne receiver is fed with two closed RF channels (FRF1 ¼ FRF2 þε), second-order nonlinear distortion causes unwanted power at baseband (f ¼ ε) at the mixer input. Again, feed-through from the RF port to the baseband port of the mixer creates overlapping of unwanted power on the wanted channel at baseband. Despite these technical challenges, the monolithic integration of homodyne receivers allowed major breakthrough within the cellular phone industry [32, 33].
3 Analog-to-Digital Conversion 21 ϕ1 φ1 sub-ADC TH sub-ADC in(t) Dig mux out(nT) sub-ADC TH φM sub-ADC ϕN Fig. 28 TH hierarchy In , a 40 GSps 6-bit ADC using 16 SAR ADCs is presented. In order to preserve the input bandwidth, the TH circuits are split into 2 banks of 8, driven through a 6-dB loss power splitter. In high-resolution ADCs, as the TH input capacitance increases (dictated by KT/C noise), only few TH units can be parallelized in order to preserve the input BW and minimize BW mismatches.