Circuit Techniques for Low-Voltage and High-Speed A/D by Mikko E. Waltari

By Mikko E. Waltari

For 4 many years the evolution of built-in circuits has Moore’s legislation, in accordance with which the variety of transistors according to sq. millimeter of silicon doubles each 18 months. whilst transistors became quicker, making attainable ever-increasing clock charges in electronic circuits. This development turns out set to proceed for a minimum of one other decade with no slowing down. hence, within the close to destiny the processing strength of electronic circuits will proceed to extend at an accelerating velocity. For analog circuits the evolution of know-how isn't really as necessary. hence, there's a pattern to maneuver sign processing services from the analog area to the electronic one, which, along with taking into consideration the next point of accuracy, offers discounts in strength intake and silicon sector, raises robustness, accelerates the layout method, brings flexibility and programmability, and raises the chances for layout reuse. in lots of functions the enter and output indications of the approach are inherently analog, combating all-digital realizations; at least a conversion among analog and electronic is required on the - terfaces. quite often, relocating the analog-digital boundary towards the surface global raises the bit cost throughout it. In telecommunications structures the rage to spice up bit charges is predicated on - ploying widerbandwidths and a better signal-to-noise ratio. whilst radio architectures in lots of functions are evolving towards software-defined radio, one of many major features of that's the moving of the anal- electronic boundary towards the antenna.

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6. For example, when the coarse A/D conversion tells us that the signal is between the first stage reference voltages and the taps in range 3 are used as fine references. A/D Converters 37 Subranging architecture allows for higher resolutions than the flash method, thanks to the reduced number of comparators. It cannot achieve as high a speed because of the S/H circuit that is needed and the fact that the fine ADC can operate only after the coarse result is available. The architecture does not alleviate the comparator accuracy requirement, unless inter-stage gain is introduced.

During clock phase it samples the input voltage into two nominally equally-sized capacitors and In the second phase the capacitor is connected in a feedback loop around the amplifier and the capacitor to one of the three reference voltages, according to the output of the stage’s sub-ADC. The resulting output voltage is given by: where Q is the ADC output code with possible values –1, 0, and +1. 2), is obtained with equal capacitor values. 47 A/D Converters If there is mismatch in the capacitor values, being and the gain will be instead of instead of 2 and the reference voltage Similarly, a finite opamp gain will reduce the gain to 2 · and the reference voltage to where A is the opamp gain and the capacitance from the negative opamp input node to the ground.

1 Problems and Solutions The problems of time-interleaved architecture arise from channel mismatch. The channels may have different offset voltages, their absolute gains can be different, or there can be a constant skew in the clock signals [90]. How these errors are seen in the spectrum of the sampled signal will be discussed in conjunction with the double-sampling technique in Chapter 9. Up to a certain resolution, component matching is good enough and the errors can be kept to a tolerable level with careful design.

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