Design of Interconnection Networks for Programmable Logic by Guy Lemieux

By Guy Lemieux

Programmable good judgment units (PLDs) became the foremost implementation medium for the majority of electronic circuits designed this present day. whereas the highest-volume units are nonetheless outfitted with full-fabrication instead of box­ programmability, the craze in the direction of ever fewer ASICs and extra FPGAs is apparent. This makes the sphere of PLD structure ever extra vital, as there's better call for for swifter, smaller, more cost-effective and lower-power programmable common sense. PLDs are ninety% routing and 10% common sense. This e-book makes a speciality of that ninety% that's the programmable routing: the style within which the programmable wires are hooked up and the circuit layout of the programmable switches themselves. somebody looking to comprehend the layout of an FPGA must develop into lit­ erate within the complexities of programmable routing structure. This publication builds at the state of the art of programmable interconnect through supplying new equipment of investigating and measuring interconnect constructions, in addition to new programmable change uncomplicated circuits. The early element of this publication offers an exceptional survey of interconnec­ tion buildings and circuits as they exist this present day. Lemieux and Lewis then offer a brand new approach to layout sparse crossbars as they're utilized in PLDs, and express that the tactic works with an empirical validation. this is often certainly one of a number of routing structure works that hire analytical the way to care for the routing archi­ tecture layout. The research allows attention-grabbing insights now not as a rule attainable with the normal empirical approach.

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Summary Except for the design of concentrators and nonblocking graphs using expanders, all of the network constructions shown in this section have been constructed from full crossbars. The ability of full crossbars to use all their outputs, or to fully permute their outputs, are often essential for the design of these networks. In contrast, PLD routing networks can often tolerate operating at reduced capacity or with relaxed signal order restrictions. One common trend across the many network designs is that the number of switches can be reduced by using more interconnect stages.

These two steps are described in greater detail below. Interconnect delays for each net are computed using the Elmore delay method [Elm48], which works well for RC trees. In this computation, wires and unbuffered switches are modeled as RC elements. In addition, the Elmore delay computation is augmented to allow buffers inside the RC tree [OC92]. This involves replacing each buffer with a constant delay element, a voltage source, an output resistance, and input and output capacitors. At the inputs and outputs of a CLB, the Elmore delay computation ends and a constant delay model is used instead.

That work also found that increasing the spacing between the metal routing wires is more effective at reducing delay than widening them. More recent work by Roopchansingh [Roo02, RR02] introduces nearest-neighbour connections between adjacent CLBs to improve delay by roughly 7%. 2 Mesh Architecture Model Details In addition to the architectural description above, there are a number of important details that can affect the flexibility of the routing network or the suitability for implementation.

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